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Date Announcement
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Important Dates

 

Important Dates
  • Submission deadline: May 24, 2026
  • Notification of acceptance: Aug. 31, 2026
  • Camera ready manuscript: Sep. 30, 2026



Conference Overview

The IEEE 35th Asian Test Symposium (ATS 2026), a premier international forum in the field of electronics testing, will be held at the Hotel Nikko Kaohsiung in Taiwan from November 18 to 20, 2026. This conference serves as a pivotal platform for academic researchers and industry professionals from around the globe. Its primary objective is to facilitate the exchange of groundbreaking ideas and the presentation of the latest research findings. We cordially invite the submission of original papers covering all aspects of system, module, and device testing, as well as broader test technologies.

Global Network

Connect with researchers and professionals worldwide

Innovation Exchange

Share groundbreaking ideas and latest research

Paper Submissions

Submit original papers on testing technologies

Call for Papers

The ATS 2026 Organizing Committee invites original, unpublished paper submissions on the topics listed below. Regular paper submissions should be made electronically by PDF manuscripts only, not exceeding 6 pages in IEEE 2-column format (including abstract, figures, tables, and bibliography). A submission will be considered evidence that upon acceptance, at least one author will attend the conference to make the presentation. Authors of accepted papers are also responsible for preparing the final manuscripts in time to be included in the electronic proceedings, which will eventually be published in IEEE Xplore Digital Library. At least one full registration to the conference is required for each accepted paper. More information is available from the following link: Submission Guidelines.

Requirements
  • 6 pages maximum
  • IEEE 2-column format
  • PDF format only
  • Original work
  • Author attendance
  • Full registration

Topics — Original papers on, but not limited to, the following areas are invited:

  • AI test and Test for AI
  • Analog/Mixed-Signal Test
  • ATE Design
  • Automatic Test Pattern Generation (ATPG)
  • Autonomous Testing
  • Board-Level Testing and Diagnosis
  • Boundary Scan Test
  • Built-In Self-Test (BIST)
  • CPU/GPU Test
  • Connectivity Testing
  • Defect-Based Test
  • Delay and Performance Test
  • Dependability and Functional Safety
  • Design Verification, Validation, and Debug
  • Design for Testability (DFT)
  • Diagnosis and Silicon Debug
  • Fault Diagnosis and Failure Analysis
  • Fault Modeling and Simulation
  • Fault Tolerance
  • Hardware Oriented Security and Trust
  • High-Speed I/O Test
  • Heterogeneous Testing
  • Low-Power IC Test
  • Machine Learning in Test
  • Memory Test, Diagnosis, and Repair
  • Multi-/Many-core Processor Test
  • Online Test
  • On-Chip Measurement
  • Power/Thermal/Reliability Issues in Test
  • Reconfigurable System Test
  • Reliability and Testing for Emerging/Approximate/Quantum Computing
  • RF Test
  • Safety and Test for Automotive ICs
  • Self-Repair
  • SiP, Chiplet, 2.5D and 3D IC Test
  • Software Test and Reliability
  • Standards in Test
  • System-on-Chip Test
  • Test Compression
  • Test Economics
  • Test Quality
  • Test Synthesis
  • Test for Biomedical Circuits and Systems
  • Test for MEMS and Microfluidic Systems
  • Test for Nanoscale Devices and Emerging Technologies
  • Test for Reversible and Quantum Circuits
  • Test for Sensors and IoT
  • Yield Analysis, Learning, and Enhancement

Conference Organizers