The explosive growth of artificial intelligence (AI) applications is driving unprecedented advances in semiconductor technology, including advanced process nodes, heterogeneous multi-die integration, high-speed interconnects, and optical networking. As a result, modern AI systems deployed in data centers have become orders of magnitude more complex than those of only a few years ago. However, semiconductor test methodologies have struggled to keep pace with this rapid evolution, creating a growing bottleneck in achieving scalable, reliable, and cost-effective AI infrastructure.

This challenge extends beyond manufacturing test to reliability and in-field tests. AI systems today experience significantly higher failure rates, while the burden of system-level test (SLT), qualification, and reliability assurance increasingly falls on cloud service providers (CSPs). Addressing these challenges requires coordinated innovation across the entire semiconductor and system ecosystem. A key enabler is the transition from traditional pass/fail testing toward comprehensive silicon health assessment throughout the product lifecycle from manufacturing to the field. Leveraging silicon lifecycle management (SLM) technologies, health-monitoring data can be used to drive system-level adaptation, improve operational reliability, and maximize resource utilization. This "shift-left" approach redistributes test intelligence closer to silicon, reducing overall test cost while enhancing end-system reliability.

At the same time, production-scale SoCs continue to increase in size, hierarchy, and test complexity, making it increasingly difficult to achieve optimal test quality of results (QoR). Conventional DFT and ATPG configuration exploration remains highly iterative and time-consuming. Evaluating a single candidate often requires restarting large portions of the flow, including DFT planning, synthesis, scan implementation, ATPG collateral generation, and ATPG execution, resulting in turnaround times ranging from several days to more than a week for a major retuning cycle.

To address these challenges, this session presents AI-enabled methodologies based on the Unified TestMAX Platform and TSO.ai technology. AI-assisted DFT planning automates pre-ATPG preparation and efficiently identifies high-quality test configurations, while AI-driven ATPG optimization automates parameter tuning and minimizes manual trial-and-error. Production deployments on large-scale SoCs have demonstrated more than 50% test-time reduction while significantly shortening optimization cycles and improving engineering productivity.

Looking beyond optimization, the session explores how AI technologies are reshaping the future of semiconductor test engineering. AI-assisted workflows are enabling higher levels of automation, accelerating debug, improving decision-making, and laying the foundation for autonomous test engineering. Combined with enhanced silicon observability, health monitoring, and closed-loop feedback mechanisms, these innovations are extending test from a manufacturing activity to a continuous reliability-management framework throughout system deployment.

Through practical industrial case studies and production-proven deployments, attendees will gain insights into the evolution of semiconductor testing in the AI era, from AI-driven optimization and engineering automation to reliability-aware operation of next-generation AI systems. This session provides a forward-looking roadmap for transforming semiconductor test into a strategic enabler of future AI infrastructure.