Select a presentation ID or paper title to view the abstract and available keywords.

RS2

Multi-Die Security

December 2, 2026 (Wednesday) 13:40–14:40 Banquet Ballroom C+D

RS2 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS2-1 (3)	13:40–14:00	Dynamic Key Change Synchronization Scheme for Protecting Arbitrary Data Communication in a Multi-Die IC Zheng-Hao Wang1, Shi-Yu Huang1, Chi-Kang Chen2 1 National Tsing Hua University, Taiwan 2 Taiwan Electronic System Design Automation, Taiwan
RS2-2 (33)	14:00–14:20	Adaptive NI-Centered Defense Mechanism Against Black Hole Router Attacks in NoCs You-Kai Xu, Shih-Hsu Huang Chung Yuan Christian University, Taiwan
RS2-3 (55)	14:20–14:40	Hi-SDSI: Software-Defined Policy Management with Hierarchical Authentication for Secure Test Access in Chiplet Systems Hisashi Okamoto1, Senling Wang1, Hiroshi Kai1, Hiroyuki Yotsuyanagi2, Yoshinobu Higami1, Tianming Ni3, Erik Larsson4, Hiroshi Takahashi1, Xiaoqing Wen5 1 Ehime University, Japan 2 Tokushima University, Japan 3 Anhui Polytechnic University, China 4 Lund University, Sweden 5 Kyushu Institute of Technology, Japan

RS6

Timing-Aware Test

December 2, 2026 (Wednesday) 13:40–14:40 Meeting Room III+IV

RS6 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS6-1 (87)	13:40–14:00	Scalable and Efficient Timing-Aware Signal Assignment for Repairable Inter-Die Interconnects Chi-Yuan Lin, Wei-Fu Liao, Jiun-Lang Huang National Taiwan University, Taiwan
RS6-2 (54)	14:00–14:20	A Software-Controlled Phase-Swept TDC for Path Delay Measurement in FPGA-Based Processors Seito Takahashi, Satoshi Ohtake Oita University, Japan
RS6-3 (91)	14:20–14:40	GPU-Accelerated Multi-Cycle Transition Fault Simulation with Speculative FFR Grouping Dante St. Prix The University of British Columbia, Canada

RS5

Test Generation & Diagnosis

December 2, 2026 (Wednesday) 16:00–17:00 Banquet Ballroom C+D

RS5 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS5-1 (37)	16:00–16:20	Interpretable Multimodal Diagnosis of Analog Circuit Faults from Test Spectra Dapeng Yan1,2, Jiuxiang Yin1, Xin Zhang1, Yiran Shi1, Bo Hong3, Zhikuang Cai1, Xiaoqing Wen4 1 Nanjing University of Posts and Telecommunications, China 2 Nantong Institute of Nanjing University of Posts and Telecommunications, China 3 Yangzhou Yangjie Electronic Technology Co., Ltd., China 4 Kyushu Institute of Technology, Japan
RS5-2 (60)	16:20–16:40	InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning Zhiteng Chao1, Bin Sun1,2, Rengang Zhang1,2, Zizhen Liu1, Jianan Mu1, Jing Ye1,2,3, Huawei Li1,2,3 1 Institute of Computing Technology, Chinese Academy of Sciences, China 2 University of Chinese Academy of Sciences, China 3 CASTEST Co., Ltd., China
RS5-3 (43)	16:40–17:00	A Test Point Insertion Method to Increase the Estimated Number of Distinguishable Fault Pairs Based on Truncated N-to-1 Multiplexers at Register Transfer Level Yeongkyeong Yun1, Toshinori Hosokawa1, Masayoshi Yoshimura2, Koji Yamazaki3, Masayuki Arai1 1 Nihon University, Japan 2 Kyoto Sangyo University, Japan 3 Meiji University, Japan

RS9

Emerging & Approximate Circuits

December 2, 2026 (Wednesday) 16:00–17:00 Meeting Room III+IV

RS9 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS9-1 (78)	16:00–16:20	Fault-Acceptability-Aware Implication-Based Online Testing for Approximate Logic Circuits Jun-Tsung Wu, Po-Chen Ho, Tong-Yu Hsieh National Sun Yat-sen University, Taiwan
RS9-2 (76)	16:20–16:40	Analysis of Defects in Complex Cells under Multiple Input Switching Jan Dennis Reimer1, Sybille Hellebrand1, Hans-Joachim Wunderlich2 1 Paderborn University, Germany 2 University of Stuttgart, Germany
RS9-3 (65)	16:40–17:00	On Test Pattern Generator for an Approximate Multiplier with Multiple Truncation Thresholds Sumihiro Man, Yousuke Miyake, Hiroyuki Yotsuyanagi Tokushima University, Japan

RS1

Chiplet and 3D IC Testing

December 3, 2026 (Thursday) 13:00–14:00 Banquet Ballroom A+B

RS1 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS1-1 (24)	13:00–13:20	A Methodology for DL-based Fault Detection & Localization in Through-Silicon Vias Manisha Kumari1, Masahiro Fujita2, Binod Kumar1 1 IIT Jodhpur, India 2 AIST, Japan
RS1-2 (35)	13:20–13:40	A Methodology for Fault Detection & Localization in Through-Glass Vias Emphasizing Thermomechanical-related Defects Manisha Kumari1, Jaynarayan T Tudu2, Binod Kumar1 1 Indian Institute of Technology Jodhpur, India 2 Indian Institute of Technology Tirupati, India
RS1-3 (83)	13:40–14:00	BIST Scheme for Inter-Die Interconnects of Chiplet-Based Chips Yu-Chien Wang, Jin-Fu Li, Yi-Chun Huang National Central University, Taiwan

RS4

ML for Test

December 3, 2026 (Thursday) 13:00–14:00 Banquet Ballroom C+D

RS4 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS4-1 (47)	13:00–13:20	Wafer-Zone-Based Vmin Prediction for Adaptive Test Li-Yang Wang1, Ming-Ze Hsu1, Shang-Ting Lin1, James Chien-Mo Li1, Harry H. Chen2, Lin-Chien Chen2, Joy Tsai2, Ching-Ting Lin2 1 National Taiwan University, Taiwan 2 MediaTek Inc., Taiwan
RS4-2 (4)	13:20–13:40	ML-based 3DIC Transient Thermal Predictor for Fast Design Space Exploration Wei-Shen Wang1, Bing-Chen Li1, Po-Chieh Yen1, Shao-Yu Wu1, James Chien-Mo Li1, Yu-Xiang Lin1, Norman Chang2, Akhilesh Kumar2, Ying-Shiun Li2, Lang Lin2 1 National Taiwan University, Taiwan 2 Ansys part of Synopsys, United States
RS4-3 (30)	13:40–14:00	A Hamming-Transition and Fanout Feature Model for Fast Scan-Shift Power Prediction Dapeng Yan1,2, Jie Zhong1, Luping Zhang1, Dongyu Ling1, Bo Hong3, Zhikuang Cai1, Xiaoqing Wen4 1 Nanjing University of Posts and Telecommunications, China 2 Nantong Institute of Nanjing University of Posts and Telecommunications, China 3 Yangzhou Yangjie Electronic Technology Co., Ltd., China 4 Kyushu Institute of Technology, Japan

RS8

AI Fault Tolerance

December 3, 2026 (Thursday) 13:00–14:00 Meeting Room III+IV

RS8 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS8-1 (34)	13:00–13:20	VACCINE:Variation-Aware CritiCal fault Injection for robust NEuromorphic chip training Chu-Yun Hsiao, Cheng-Yun Hsieh, Jin-Wei Chen, James Chien-Mo Li National Taiwan University, Taiwan
RS8-2 (72)	13:20–13:40	Carry-Through Checksum: A Lightweight Fault-Detection for CNN Inference at the Edge Kyrylo Nazarevych1, Mohammad Hasan Ahmadilivani1, Krister Kaldre1, Davide Bertozzi2, Jaan Raik1 1 Tallinn University of Technology, Estonia 2 University of Manchester, United Kingdom
RS8-3 (50)	13:40–14:00	Reconfiguration Tree-Based Fault-Tolerant Techniques for Systolic Array-Based AI Accelerators Shyue-Kung Lu, Hong-Ruei Wu National Taiwan University of Science and Technology, Taiwan

RS3

Hardware Security

December 3, 2026 (Thursday) 14:20–15:20 Banquet Ballroom C+D

RS3 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS3-1 (8)	14:20–14:40	DR-STI: High-Throughput TRNG Based on Dynamically Reconfigurable Entropy Source and Spatio-Temporal Interleaving Architecture Lanfang Liu1, Liang Yao1, Shijiabao Huang1, Zhengfeng Huang2, Huaguo Liang2, Yingchun Lu2 1 Anhui University, China 2 Hefei University of Technology, China
RS3-2 (82)	14:40–15:00	Unsupervised RTL Hardware Trojan Detection Based on TransformerGNN Graph Autoencoder Sying-Jyan Wang1, Wei-Yi Chiu1, Katherine Shu-Min Li2 1 National Chung Hsing University, Taiwan 2 National Sun Yat-sen University, Taiwan
RS3-3 (38)	15:00–15:20	ROCKET: Ring-Oscillator-Referenced Counter-Based Framework for Path-Delay Trojan Detection Arjun Hati1, Partho Bhoumik1, Jonti Talukdar1, Jim Plusquellic2, Krishnendu Chakrabarty1 1 Arizona State University, United States 2 University of New Mexico, United States

RS7

Functional Safety

December 3, 2026 (Thursday) 14:20–15:20 Meeting Room III+IV

RS7 presentations

Presentation ID	Time	Paper Title / Authors / Affiliations
RS7-1 (25)	14:20–14:40	High-Level Synthesis of DMR-and-Retry Datapaths for Soft and Hard Error Tolerance Asahi Noma, Satoshi Ohtake Oita University, Japan
RS7-2 (27)	14:40–15:00	Dynamic Workload Selection for Ranked Fault Injection via Sequential Bernoulli Discovery Modeling Nicolò Bellarmino1, Alberto Bosio2, Riccardo Cantoro1 1 Politecnico di Torino, Italy 2 Centrale Lyon, INSA Lyon, CNRS, UCBL, CPE Lyon, France
RS7-3 (73)	15:00–15:20	System-Level-Aware RTL Criticality Analysis for Efficient Functional Safety Evaluation Yu-Hong Chao1, Ching-Han Tsai1, Jing-Jia Liou1, Harry Chen2 1 National Tsing Hua University, Taiwan 2 MediaTek Inc., Taiwan