Late Breaking Results

Select a presentation ID or paper title to view the abstract and available keywords.

LBR

LBR Short Presentation

December 2, 2026 (Wednesday) 14:40–15:40 Banquet Ballroom A+B

LBR presentations
Presentation ID	Time	Paper Title / Authors / Affiliations
	14:40–14:45	Kazuki Nakamoto¹, Toshinori Hosokawa¹, Masayoshi Yoshimura², Masayuki Arai¹ ¹ Nihon University, Japan ² Kyoto Sangyo University, Japan
	14:45–14:50	Joshua Adiel Wijaya, Poki Chen National Taiwan University of Science and Technology, Taiwan
	14:50–14:55	Yuya Koizumi¹, Toshinori Hosokawa¹, Masayoshi Yoshimura² ¹ Nihon University, Japan ² Kyoto Sangyo University, Japan
	14:55–15:00	Yasuo Sato, Shunsuke Yoshihara, Satoshi Ohtake Oita University, Japan
	15:00–15:05	Hideyuki Ichihara, Tomoo Inoue Hiroshima City University, Japan
	15:05–15:10	Yukiya Miura, Orito Matsudo Tokyo Metropolitan University, Japan
	15:10–15:15	Wei-Ji Chao, Rui-Lun Wu, Po-I Tseng, Tong-Yu Hsieh National Sun Yat-sen University, Taiwan
	15:15–15:20	Yeeren Wuang, Irving Tseng, Lisa Chen NXP Semiconductors, Taiwan
	15:20–15:25	R S Haripriya, Md Javid, Jaynarayan T Tudu Indian Institute of Technology Tirupati, India
	15:25–15:30	Hiroto Totsuka, Masayoshi Yoshimura Kyoto Sangyo University, Japan
	15:30–15:35	Satoshi Ohtake, Shiho Okadome Oita University, Japan
	15:35–15:40	Amartya Kumar, Bonthu Purna Nand, Jaynarayan T Tudu Indian Institute of Technology Tirupati, India

LBR-1 (98)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 14:40–14:45
Venue: Banquet Ballroom A+B

A Don’t Care Filling Method for Control Signals to Improve Estimated Field Random Testability at RTL

Kazuki Nakamoto¹, Toshinori Hosokawa¹, Masayoshi Yoshimura², Masayuki Arai¹

¹ Nihon University, Japan

² Kyoto Sangyo University, Japan

Keywords

field testing; built-in self-test; structural symbolic simulation; estimated field random testability; X-filling;

Abstract

In register-transfer level (RTL) design, the control signals on each state transition of controllers may contain multiple don't-cares (Xs). The way logic values are assigned to these Xs significantly affects the estimated field random testability (EFRT) of the data-path. This paper proposes a method to assign logic values to Xs in the control signals on each state transition to improve EFRT at RTL, using multiple functional time expansion models and status signal sequences that cover n-times k-consecutive state transitions. Experimental results show that the proposed method improves the EFRT by 2.35% on average compared with the X-filling performed by logic synthesis.

LBR-2 (99)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 14:45–14:50
Venue: Banquet Ballroom A+B

No-interpolator, MAC and ROM-less, non-CORDIC Sinusoidal and Gaussian Wave Generator

Joshua Adiel Wijaya, Poki Chen

National Taiwan University of Science and Technology, Taiwan

Keywords

direct digital synthesizers (DDS), digital-to-analog (DAC) circuit testing, built-in self test (BIST), sinusoidal wave generation, Gaussian wave generation

Abstract

Direct digital synthesizers (DDS) commonly rely on look-up tables to produce their outputs, but these tables consume substantial logic area and power. This work introduces a novel ROM-less sinusoidal and Gaussian waveform generator that forgoes the phase interpolator. Through differential equation approximation combined with error mitigation techniques, a 16-bit Q1.14 sinusoidal wave generator and an 8-bit UQ1.7 Gaussian wave generator are implemented on an Intel Cyclone V FPGA (5CSEBA6U23I7), operating at 200 MHz and 140 MHz, respectively. The sinusoidal wave output oscillates at 62.2 kHz with a spurious-free dynamic range (SFDR) of 77.49 dB, while the normalized Gaussian wave output exhibits a period of 283 clock cycles and a mean squared error of 3.72 × 10⁻⁴.

LBR-3 (101)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 14:50–14:55
Venue: Banquet Ballroom A+B

An Identification Method of Random-Pattern-Resistant Faults Based on Fault Detection Probability

Yuya Koizumi¹, Toshinori Hosokawa¹, Masayoshi Yoshimura²

¹ Nihon University, Japan

² Kyoto Sangyo University, Japan

Keywords

built-in self-test, random-pattern-resistant faults, don’t care Identification, binary decision diagrams, fault detection probability

Abstract

Random-pattern-resistant (RPR) faults hinder built-in self-test from achieving high fault coverage, whereas conventional RPR classifications depend on a specific test sequence or criterion. This paper proposes a test-environment-independent method for identifying RPR faults based on fault detection probability (FDP). For each fault, FDP is defined as the ratio of input patterns that detect the fault to all possible input patterns, and is computed by combining SAT-based test generation, don't-care identification, and BDD-based counting. The proposed method yields the exact probability when the enumeration is completed, and a lower bound when it is terminated before completion. Experiments on ISCAS'89 benchmark circuits demonstrate that the proposed metric identifies faults with extremely low FDP and quantitatively characterizes their resistance to uniform random patterns.

LBR-4 (102)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 14:55–15:00
Venue: Banquet Ballroom A+B

Multiple-Seed Controlled LBIST for Test Duration Reduction

Yasuo Sato, Shunsuke Yoshihara, Satoshi Ohtake

Oita University, Japan

Keywords

in-field test, LBIST, test cube, Discrete Logarithm

Abstract

In safety-critical automotive systems, achieving over 90% in-field test coverage within the ISO 26262 ASIL-D time constraints is a major challenge. This work introduces a lightweight LBIST technique that significantly shortens test time while maintaining high coverage. Across ITC benchmarks, it reduces the required patterns by 1.2×–150× at 90% coverage and by 99×–1,149× at 93%, with particularly large gains on circuits whose coverage is difficult to raise.

LBR-5 (103)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 15:00–15:05
Venue: Banquet Ballroom A+B

SC-BIST: Functional Built-In Self-Test Reusing Stochastic Number Generators and Counters

Hideyuki Ichihara, Tomoo Inoue

Hiroshima City University, Japan

Keywords

Stochastic computing, functional BIST, weighted random testing, hardware reuse.

Abstract

This paper presents SC-BIST, a functional built-in self-test framework for stochastic computing (SC) circuits. SC-BIST reuses stochastic number generators (SNGs) for weighted random test generation and counters (CNTs) for response compaction. Each stored test pattern specifies input weights, LFSR seeds, a cycle count, and reference signatures. We discuss guidelines for reducing the numbers of test patterns and cycles and for detecting faults in SNGs and CNTs. A preliminary evaluation using exact signature matching on six SC circuits achieves more than 97% main-circuit stuck-at fault coverage and more than 82% coverage including SNGs and CNTs, with at most two patterns. These results demonstrate SC-BIST’s fault detection capability on the evaluated SC circuits; area overhead and scalability remain to be evaluated.

LBR-6 (104)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 15:05–15:10
Venue: Banquet Ballroom A+B

An Initial Study on Post-Silicon Performance Recovery Using DSCT for CMOS Aging Mitigation

Yukiya Miura, Orito Matsudo

Tokyo Metropolitan University, Japan

Keywords

CMOS reliability, transistor aging (BTI, CHC), digitally controlled oscillator, propagation delay compensation, adaptive circuit design, post-silicon adjustment component

Abstract

As CMOS integrated circuits (LSIs) scale for higher performance, reliability issues like bias temperature instability (BTI) and channel hot carrier (CHC) effects become critical. These aging phenomena increase path delays, potentially leading to timing violations and silent data corruptions (SDCs). While conventional guard-banding manages these risks, it often results in excessive design costs due to over-pessimism or insufficient protection against workload-dependent variations. As a preliminary step toward establishing a systematic adaptive design methodology, this paper demonstrates the fundamental viability of using driving-strength control transistors (DSCTs)—inspired by digitally controlled oscillators (DCOs)—to compensate for aging-induced delays through post-silicon adjustments. Through LTspice simulations using a 45-nm process, we confirm that negative BTI (NBTI)-induced delay degradation can be successfully restored to initial standard values by dynamically adjusting compensation transistor sizes.

LBR-7 (105)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 15:10–15:15
Venue: Banquet Ballroom A+B

Late-Breaking Results–Std-Sel: Standard-Deviation-Guided Selective LSB Embedding for Error Detection and Quality Prediction in Quantized ViTs

Wei-Ji Chao, Rui-Lun Wu, Po-I Tseng, Tong-Yu Hsieh

National Sun Yat-sen University, Taiwan

Keywords

Vision Transformers, post-training quantization, memory reliability, soft errors, error detection.

Abstract

Quantized Vision Transformers (ViTs) reduce activation-storage cost but leave limited redundant bit space for low-overhead error protection. This work proposes Std-Sel, a standard-deviation-guided protection scheme for asymmetric UINT8 intermediate activations. Std-Sel profiles activation distributions offline and selectively embeds an LSB consistency flag only in statistically selected tail values, while preserving the dominant activation region. During deployment, corrupted values are detected through a dual distribution-and-flag check and masked to the tensor zero-point, requiring no additional activation bits. The resulting masked count is further exploited as a runtime inference-quality indicator. Experiments on four quantized ViTs show that Std-Sel incurs substantially lower error-free accuracy loss than unconditional parity and improves Top-1 accuracy by approximately 4% to 33% over the unprotected baseline at a BER of 10⁻⁴. The masked count also provides more reliable inference-quality prediction than parity- and range-based indicators.

LBR-8 (106)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 15:15–15:20
Venue: Banquet Ballroom A+B

An Explainable AI-Agent Framework for Semiconductor Test Data Analysis and Root-Cause Identification

Yeeren Wuang, Irving Tseng, Lisa Chen

NXP Semiconductors, Taiwan

Keywords

AI agent, semiconductor testing, yield analysis, root-cause identification

Abstract

The increasing complexity of semiconductor devices has substantially expanded the volume and diversity of manufacturing and automatic test equipment data generated during product qualification and mass production. Conventional yield-loss investigation relies heavily on manual data inspection, statistical scripting, and individual engineering experience, resulting in long analysis cycles and inconsistent conclusions. This work presents an explainable AI-agent framework that integrates heterogeneous test-data processing, statistical analysis, machine-learning inference, and evidence-based reasoning into a unified decision-support workflow. The framework converts raw ATE data into structured engineering features, detects anomalous spatial and parametric patterns, evaluates correlation and historical evidence, and ranks candidate root-causes for engineering verification. The approach was evaluated using data from 250 wafers across 10 lots and approximately 10,000 test parameters from multiple automotive products and temperature conditions. On the evaluated investigation cases, the framework achieved 90% top-ranked root-cause agreement with engineer-verified investigation results and reduced analysis time by up to 8x -16x compared with the conventional engineering workflow involving manual data extraction, script execution, and sequential investigation. Two industrial case studies demonstrate site-level failure localization and correlation-based investigation of LOI power and VGA-gain behavior. These results demonstrate that the proposed framework provides a practical, traceable, and locally executable solution for semiconductor test-data analysis and engineering root-cause investigation.

LBR-9 (107)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 15:20–15:25
Venue: Banquet Ballroom A+B

Criticality Analysis and Test Methodology for Weight Bit-Flip Faults in Deep Q-Networks on GPUs

R S Haripriya, Md Javid, Jaynarayan T Tudu

Indian Institute of Technology Tirupati, India

Abstract

Reinforcement learning (RL) agents are commonly trained on GPUs, where the weights could get corrupted by bit flips from soft errors or from Rowhammer in DDR/GDDR memory. We study single-bit faults in the weights of a Deep Q-Network (DQN) that keep all values finite and thus escape a finiteness check. We define a fault as critical if it reduces the mean return over 20 paired episodes by more than 10% of the task’s reward range, with a one-sided Wilcoxon signed-rank test giving p < 0.05. On two control tasks, we evaluate 11,389 faults without retraining and 471 training runs, each paired with a fault-free run under common random numbers and compared with a control group of flips in the least significant mantissa bit. In our experiments, exponent bits accounted for 77% of the critical faults. Comparing the selected actions of the faulty and fault-free networks on 256 stored probe states detected 98-100% of the critical faults and flagged 12% of the benign ones, whereas weight-range and Q-value checks missed all critical sign and mantissa faults. During training, 59% of the exponent-MSB faults became non-finite, the remaining silent faults did not degrade training significantly more often than the control group.

LBR-10 (109)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 15:25–15:30
Venue: Banquet Ballroom A+B

Hardware Trojan Detection Method in RTL Design with Graph Isomorphism Network

Hiroto Totsuka, Masayoshi Yoshimura

Kyoto Sangyo University, Japan

Keywords

Hardware Trojan, RTL Design, Graph Isomorphism Network, Abstract Syntax Tree

Abstract

The decentralization of the LSI supply chain has heightened the threat posed by malicious Hardware Trojans (HT). To implement effective countermeasures, HT detection at the Register Transfer Level (RTL) is essential. In recent years, Graph Neural Networks (GNNs) based detection methods have been considered effective. However, structural information tends to be lost during the aggregation process, which often obscures the subtle features specific to HT. In this paper, we propose an advanced HT detection method utilizing Graph Isomorphism Networks (GINs) to address this challenge. By extracting an Abstract Syntax Tree (AST) from the RTL description, we construct a graph that retains all syntactic and hierarchical information. GINs accurately learn these topological features without any loss of information. Evaluations using the Trust-Hub dataset and our proprietary dataset confirmed that the proposed method achieves higher detection accuracy than conventional GNNs.

LBR-11 (111)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 15:30–15:35
Venue: Banquet Ballroom A+B

An FPGA Implementation of Faster-than-at-Speed Test Clock Generation for Application-Specific Timing-Margin Evaluation

Satoshi Ohtake, Shiho Okadome

Oita University, Japan

Keywords

FPGA, faster-than-at-speed testing, test-clock generation, launch-off-capture, timing margin

Abstract

This paper presents an FPGA implementation of faster-than-at-speed (FAST) clock generation for scan-based launch-off-capture testing. A PLL and a capture-pulse generation circuit were implemented on a Cyclone V FPGA with a scan-inserted RISC-V processor. Frequency-sweep and temperature-chamber experiments revealed pattern- and temperature-dependent timing behavior. Oscilloscope measurements confirmed the intended capture pulses at 50 and 131 MHz. The results support FAST-based timing-behavior sensing; aging-induced degradation remains unvalidated.

LBR-12 (112)

LBR Short Presentation

Date: December 2, 2026 (Wednesday)
Time: 15:35–15:40
Venue: Banquet Ballroom A+B

Downstream-Aware Fault Ordering for ATPG Data

Amartya Kumar, Bonthu Purna Nand, Jaynarayan T Tudu

Indian Institute of Technology Tirupati, India

Abstract

Pattern count is an incomplete proxy for encoded test data volume when ATPG outputs undergo reordering and compression. We investigate whether multiple fault ordering (MFO) already produces candidates that expose this mismatch. Compression cost aware MFO (CA-MFO) retains the existing FAN candidate generation process and selects among candidates by fault coverage, followed by encoded bit count after Hamming distance reordering, previous-pattern XOR, and frequency directed run length coding. Across 12 ISCAS’89 circuits, CA-MFO reduces encoded volume on five circuits by up to 7.56%, with unchanged reported fault coverage. Aggregate encoded volume decreases by 0.81%, while aggregate pattern count increases by 2.46%. All five improving candidates contain more patterns than their standard-MFO counterparts; they also improve under a separate static-Huffman evaluation. Reported aggregate runtime increases by 3.67%. These preliminary results demonstrate that existing fault-ordering diversity can expose a trade-off between pattern count and encoded volume, motivating downstream-aware candidate selection.