Fault injection (FI) enables systematic evaluation of the effects of single-event upsets (SEUs) and other soft errors, as well as the effectiveness of error-handling mechanisms. A key constraint is the availability of design information and access to internal state. Commercial off-the-shelf (COTS) devices often restrict FI to externally accessible state or indirect models of hidden structures; custom-designed chips can additionally exploit netlists, scan chains, and field-programmable gate array (FPGA) prototypes. Within either setting, the fault model, injection timing, throughput, and failure criteria govern how results should be interpreted. This paper reviews selected FI approaches for processors and AI systems-on-chip (SoCs), including cache-fault emulation, scan-based injection, hardware acceleration, campaign reduction, timing control, and circuit-to-system fault propagation. Fault scenarios include conventional bit upsets and, where warranted, correlated upsets and flip-flop (FF) errors induced by logic transients. The discussion connects design accessibility, fault-model assumptions, execution efficiency, and validation evidence to the design and interpretation of FI campaigns.

While Deep Neural Networks (DNNs) have transformed computing paradigms, assessing the hardware reliability of specialized AI accelerators remains a critical challenge. The physical complexity of modern accelerators, coupled with the probabilistic nature of DNN execution, makes tracing low-level hardware faults to high-level software errors difficult. Transient faults in shared hardware logic—such as schedulers or arithmetic units—can induce complex, multi-thread error patterns distinct from simple memory bit-flips. Furthermore, experimental results can be heavily biased by specific input frames and model training quality. To address these challenges, this paper presents a comprehensive reliability assessment framework that integrates physical beam experiments, multi-level fault injection, and application-level vulnerability analysis. By combining these complementary methodologies, we establish realistic fault models, map error propagation pathways across hardware-software boundaries, and accurately quantify the impact of radiation-induced faults on next-generation AI accelerators.

Process scaling makes memory more error-prone, while ever-larger AI models give each error more ways to propagate. Memory error-correcting codes (ECCs) can keep AI infrastructure reliable, but HBM and LPDDR afford little redundancy per access. We argue that the limit lies less in how much redundancy is available than in how it is spent. Cerberus goes beyond the boundaries between on-die, link, and system ECC, which today duplicate redundancy, add latency, and can undermine one another through miscorrections. It encodes data once at the memory controller and lets every layer reuse the same redundancy, cutting HBM4-class storage redundancy by 33.3% while correcting multi-location errors that layered designs cannot. RangeGuard goes beyond bit-exactness: since DNNs tolerate small value changes but not extreme outliers, it protects each value’s numeric range instead of its bits. Within today’s 16 parity bits per 32-byte block, it tolerates errors spanning 64+ bits and keeps large language models near fault-free accuracy at bit error rates up to 10⁻⁷–10⁻⁶, versus 10⁻¹⁰ without protection.