What happens when chips pass conventional tests but still contain critical defects? As CMOS scales and emerging memories introduce new failure mechanisms, traditional fault models can miss the physical behaviors that determine silicon quality and reliability.

This tutorial introduces Device-Aware Test (DAT), a patented methodology that connects physical defect mechanisms, device modeling, fault analysis, and test generation to expose defects overlooked by conventional approaches. Drawing on more than eight years of research and industrial collaboration, it presents DAT’s foundations, practical workflow, and industrial silicon validation, including results obtained with imec and STMicroelectronics chips. Applications span STT-MRAM, RRAM, FeFET, and advanced CMOS technologies.

Attendees will gain practical insights into how device physics can guide more effective tests, reduce test escapes and overtesting, and improve outgoing quality. The tutorial concludes with deployment challenges, recent advances, and research opportunities toward zero-defect manufacturing.

Said Hamdioui is Chair Professor of Dependable and Emerging Computer Technologies and Head of the Computer Engineering Laboratory at Delft University of Technology, the Netherlands. His research focuses on memory testing, hardware reliability, emerging memory technologies, and in-memory computing. He pioneered Device-Aware Test technology to address the limitations of conventional semiconductor testing. In 2025, he received a highly competitive €2.5 million European Innovation Council grant to support the commercialization of this technology. He is a Fellow of the Netherlands Academy of Engineering and a recipient of the EDAA Outstanding Dissertation Award for his pioneering work on memory testing. Before joining TU Delft, he worked at Intel, Philips Semiconductors, and NXP.

Scan test diagnosis is critical to physical failure analysis success rate. This tutorial will cover recent progress in diagnosis automation. It includes a pre-silicon design-for-diagnosis system to identify and resolve design and scan test bottlenects to meet physical failure analysis success rate.

Wu-Tung Cheng (Life Fellow, IEEE) received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, in 1978 and 1982, respectively, and the Ph.D. degree in computer science from the University of Illinois at Urbana–Champaign, in 1985. From 1985 to 1990, he was with AT&T Bell Laboratories. From 1990 to 1993, he was a Co-Founder of CheckLogic System, Inc., and was the Vice President of Engineering. In 1993, CheckLogic was merged with Mentor Graphics Corporation, which was acquired by Siemens in 2016. He has had various technical and management positions in design for the test area until 2025. From 2026, he is a distinguished professor at National Tsing Hua University and a visiting professor at National Taiwan University. He has published over 185 research papers in the test and diagnosis areas, with 87 granted patents and 11 pending patents